1. Field of the Invention
The present invention generally relates to the manufacture of integrated circuits in silicon wafers and, more particularly, to the correlation of the large scale topography of a semiconductor wafer to the characteristics of devices subsequently formed on the wafer. Where significant correlations are found, the large scale topography of subsequent wafers are modified to optimize device characteristics and yield.
2. Description of the Prior Art
In the manufacture of large scale integrated (LSI) circuits, there are various factors which contribute to increased circuit density. Among these are reductions in feature size and an increase in device and circuit complexity. The greater circuit densities are being achieved with the use of several types of transistors on a single chip, allowing for greater design flexibility. The varying transistor types as well as their closer proximity require improvements in device isolation. Current technology, however, does not explain isolation and device junction leakage related failures in some device structures. It is important to address this problem since it is an important factor in both increased circuit density and product yield.